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Thermo-Mechanical Analysis Methods for Printed Circuit Boards: Part 2

Representative QFP Geometry & Mesh | FEA Consulting
May 2, 2017 By: Michael Kuron

In part one of this series, I discussed modeling approaches for the complex geometry found in printed circuit boards. In this post, I’ll discuss methods for characterizing the thermal properties of integrated circuit (IC) packages. Analysis of IC packages is critical at many levels of the design process, including package level thermal design, board level modeling including heat sink designs and package viability, as well as system level flow and thermal characterization. Much like a PCB, IC packages are geometrically complex, with disparate length scales that are challenging to explicitly capture in an analysis.

Figure 1 – Typical IC Packages1


One of the primary interests when performing a thermal analysis of a system that includes an IC package is determining the junction temperature, to ensure that our designs operate at temperatures that will not cause damage to the system. To do so, our models must capture the various heat pathways through a package, including conduction from the die through the internal layers; convection and radiation from the surface; and heat transfer to the board on which the package sits. So, with that goal in mind, how can we efficiently model the thermal characteristics of an IC package? I’ve outlined 5 methods of varying complexity and accuracy below:

Method 1: 2D Source

The most basic approach to modeling an IC package is to apply the heat dissipated by the package as a 2-dimensional source on the surface of the board. This approach will provide no explicit information about the die temperature, and therefore requires the analyst to back out the junction temperature based on the predicted local board temperature. This is among the least accurate of all modeling choices, but also requires the smallest computational expense. In large system level models, this approach can be used with success to understand global heat transfer rates and characteristics.

Method 2: Lumped Material Properties

A second simplified approach is to represent the package in 3D using its geometric bounding box, while assigning an effective, uniform set of thermal properties. Since most IC packages are comprised of a common set of materials, the analyst can estimate their volumetric proportions to compute effective thermal conductivities and densities, similar to the methodology for PCB’s presented in the first of this blog series. As with method 1, the lumped material properties is limited in its accuracy, but may be useful for large system level models in which the obstruction of flow due to components is important.

Method 3: Thermal Resistor Networks

For analyses aimed at predicting the junction temperature of components, the heat transfer pathways within the package must be modeled in some way. As shown in Figure 2, one approach for doing so is to construct a network of thermal resistors from the die to the exterior of the package, including conduction to the board and convection to the ambient surroundings. These thermal networks can be constructed in great complexity where necessary to capture the intricate pathways within a package. In general, however, most analysts rely on simple two resistor networks that account for the thermal resistance from the junction to case, and junction to board. Regardless of their complexity, network models have the great advantage of being much more computationally efficient than other methods of capturing the heat transfer pathways within an IC package, as the mesh requirements are minimal.

Figure 2 – Generic Chip Thermal Resistor Network (left), Simplified 2 Resistor Thermal Network (right)

Many chip suppliers will provide thermal resistance values for their components on their respective data sheets, and some may even provide more complex DELPHI multi-resistor network models. For suppliers that do not publish thermal resistance values, ANSYS Icepak has a macro that can be used to predict these thermal resistances using the detailed package geometry and the JEDEC test standard. My experience has found that supplier provided values tend to be conservative, and that the junction to board values in general are sensitive to the local board properties. However, simplified thermal resistor networks provide an efficient and accurate way of characterizing thermal performance for both system and board level models.

Method 4: Compact Conduction Models

A second approach to characterizing the thermal pathways in an IC package is to simplify the major components (i.e. a solder ball array) into a block with orthotropic conductivity. - major pathways modeled, uses simplified geometry. This approach requires knowledge of the package geometric details, but can result in accurate prediction of the package behavior if the simplified model is validated against a detailed representation of the geometry.


Figure 3 – Detailed IC Package Cross-section (left). Compact Conduction Model Simplification (right)


As with the thermal network approach, ANSYS Icepak offers a macro that can be used to generate a compact conduction model from a detail geometric representation of a package. Since this methodology models the simplified package layers explicitly, the mesh requirements are more cumbersome than the thermal network approach. As such, this methodology is most useful for board level analyses where the demands of increased accuracy warrant the additional computational expense.

Method 5: Detailed Package Models

The most accurate approach to package modeling, as well as the most computationally expensive, is to model the 3D package geometry explicitly. This method allows the analysts to directly capture the heat transfer pathways from the die to the board and ambient. Detailed package geometry can typically be imported from ECAD sources, or developed by the analyst themselves (note: ANSYS Icepak has macros to build typical package geometries!).

Figure 4 – Representative QFP Geometry and Mesh


Due to the geometric complexity, a single IC package may require a mesh of greater than 1 million cells! As such, this level of detail is typically only practical for package level thermal design analyses.

In the next part of this series we will discuss vibration analysis methods for PCB’s – stay tuned!

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References

1. http://electroiq.com/blog/2005/08/materials-and-methods-for-ic-package-a...