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Choosing the Right Ports for Your Signal Integrity Analysis
When setting up an analysis in order to verify critical transmission lines on your PCB layout, the input and output terminals of the trace geometry are defined using ports. HF EM simulators usually provide alternate methods for assigning ports. The port provides a way to connect an excitation to the transmission line under analysis and it is the ports to which a set of S-parameters will be referenced and generated.
Real world transmission lines terminate into IC pins, connector pins and passive component pads. Sometimes the termination point is a juncture of a pin and a via; in other instances, the termination point is just a pad. The requirements of your analysis will drive how you choose the simulation port type:
1) Main transmission line analysis only
2) Main transmission line + the component transition to the PCB trace as the analysis set.
Main Transmission Line Analysis
If we are concerned about the PCB transmission line features only, we should then be concerned about how our ports interact with the trace as is the case for this blog post. Below is an example of a single-ended micro-strip PCB trace. One end of the trace terminates at a BGA pin PCB pad. The other end terminates at the PCB edge.
Figure 1: Single Ended Microstrip Trace with BGA Pads
Figure 1 shows a microstrip trace being set up for analysis. On the left end of the trace is a “wave” port capturing the TEM wave propagation. On the right side are the BGA pads, six pads representing ground, power and the signal pin connections to the BGA. No port has been assigned to this end of the trace.
Electronics simulation software generally provides options of the types of port to choose. For example, in ANSYS HFSS 3D layout, depending on the PCB situation, one can choose from:
- Coax Gap port (vertical structures)
- Gap port for (horizontal structures, i.e. component pad)
- Wave port (vertical structures)
- Gap port (vertical structures)
Below 1GHz, all of these port implementations perform essentially the same without much tweaking. However, at higher frequencies, careful attention to the geometry of the port needs to be considered to minimize the following parasitic effects:
1) Inductance in the signal path
2) Capacitance to ground in the signal path
3) Inductance in the return path
Without delving into an in-depth mathematical analysis, it is sufficient to say that these circuit parasitic elements can create an impedance discontinuity in the transmission line. The characteristic transmission line impedance is represented by Zo. Deviations from the target system impedance to Zo cause a mismatch between Zo and the termination impedance creating artificial transmission losses through reflections and subsequent degradation of frequency response. Some of these effects are contributed by the pad to which the component pin is soldered to, and some from the device package itself. But in this post, we are focusing on the simulation port contribution.
Matching Port Type to Component Geometry
A properly sized wave port (Figure 5), introduces the least amount of these parasitic effects. But a wave port is only practical to use when the transmission line terminates at the edge of the trace, or if your concern is the performance of the trace segments and not the trace plus the transition into a connector or component footprint. Alternatively, SMT (Surface Mount Technology) devices would require the use of a Gap port or a Coax Gap port.
Typically, today’s high speed PCB transmission lines terminate into an SMT IC package such as a BGA, QNF or gull wing. A BGA (Ball Grid Array) package is a common package used in advanced network ICs with the high-speed interfaces on the ball contact pins at the perimeter of the device. This is so the transmission lines can launch onto the surface layer of the PCB as microstrip transmission lines as opposed to Stripline geometry on an inner layer. The signal pins should be surrounded by ground pins to maintain the best continuity in the return path. A Coax wave port tends to be the best fit for this application.
Right Sizing a Coax Wave Port
Figure 6 is a cross-section of a PBC and BGA IC. This simplified illustration shows the BGA solder ball touching the PCB pad for the signal and ground connections. The ground connection is directly connected to a via, that is also connected to all ground layers. In real scenarios, there might be a “dog bone” shaped trace that offsets the ground via from the IC pad. In this example, the via is part of the IC pad which reduces ground path inductance. The BGA signal pad is where we need to position our port.
Figure 6: PCB Stackup with BGA
In creating this Coax Wave Port, a PEC (Perfect Electrical Conductor) layer is implemented in order to raise the ground to the level of the ground where the port is to be referenced as shown in Figure 7. This allows the excitation to enter the top pad through the port and the connecting via and have a uniform ground reference without shorting out the trace.
The problems introduced at this interface are contributed by the port implementation and the BGA pad itself:
- BGA PCB pad size – tends to lower Zo with increasing pad diameter.
- PEC layer height - Increases port inductance with greater height, potentially raises port capacitance with less height above PCB surface.
- Port via hole diameter – Increases Zo with decreasing diameter.
- Port aperture diameter - Decreasing Zo with increasing diameter.
- PEC layer overlap with top layer trace – PEC to trace capacitance lowers Zo in the overlap area.
The BGA pad diameter is determined by the BGA ball size as required by the IC manufacture, so this is a PCB feature which will not be adjusted in this discussion, since we are only examining the port definition. PEC layer height, port via hole diameter, port aperture diameter, and PEC layer overlap are constructs of the port itself and can be optimized to minimize errors due to port implementation.
Figure 8 shows the frequency response (S21) of a 0.5” trace attached to a Coax Wave port at the BGA end and a wave port at the board edge. The resultant plot lines are for various combinations of PEC layer height (.005” to .010”) and port aperture (.015” to .020”). As these quantities are changed, the frequency response changes. The changes to the frequency response can be seen in the overall change in loss and also seen in the “waviness” of the response. This waviness observed is indicative of impedance mismatches along the length of a transmission line, called Insertion Loss Deviation (ILD). Contributors to ILD include the geometries of the trace, pad and port. For this example, it turns out that a 6mil gap and 20mil PEC aperture diameter, produces the lowest ILD, indicating that the port inductance at the 6 mil air gap has compensated for the 20 mil port pad capacitance. The TDR plot in Figure 9 clearly shows the impedance disruption at the coax wave port location. By sweeping the air gap we can see that the shortest recovery from the impedance dip also occurs at the 6mil gap setting.
Figure 8: Coax Wave Port S21 at Different PEC Air Gaps
Figure 9: TDR at Various Port Air Gaps
If we change our focus to the via that connects the PEC pad to the top layer BGA pad, we can determine the optimum via diameter. The optimal values obtained from the previous study (6mil gap and 20mil PEC aperture diameter) are used for this analysis. The parametric sweep of via diameter from 5 to 10mils in Figure 10 and Figure 11 show (with the yellow tag) that the optimum via diameter is 7mils.
Figure 10: S21 Parametric Sweep of Via Drill Diameter
Figure 11: TDR Parametric Sweep of Via Drill Diameter
There is an unavoidable overlap of the PEC layer over the portion of the microstrip trace as it enters the BGA pad. This overlap, in conjunction with the PEC air gap provides another capacitive coupling to ground causing an additional impedance discontinuity. Minimizing this overlap will further reduce the impedance discontinuity at the port interface. With air gap set to 6 mils, a 20mil PEC aperture diameter, and a 7 mil via hole diameter, the final step is to optimize this PEC layer overlap. Figure 12 shows the definition of this quantity.
Figure 12: PEC Layer to Signal Trace Overlap
Unsurprisingly, as shown in Figure 13 and Figure 14, the best performance is with the overlap at a minimum.
Figure 13: S21 Parametric Sweep of PEC Layer X Edge
Figure 14: TDR Parametric Sweep of PEC Layer X Edge
In summary, by using a systematic, parametric approach to designing the port, I was able to come up with a port configuration which minimizes the numerically-induced artificial impedance discontinuity at the BGA port location. A comparison of TDR plots in Figures 9 (initial configuration) and 14 (optimized configuration) shows the improvement to be approximately 15W.
The most important message of this post is to always consider the port contribution to distortions in your results. This is especially important at high frequency. Using a “standard” to compare with your PCB transmission will lend credibility to your results. If your transmission line has bends, twists and turns, you may want to build a “perfect” transmission line model; that is a TL with all the same geometry and properties, but straight with a predetermined length. In this environment, the remaining distortions will be at the ports. I use ANSYS HFSS software which gives me the ability to use a wave port at one end of perfect model to isolate any distortion to the remaining port in order to make adjustments. The techniques demonstrated here demonstrate common sense transmission line adjustments that correlate to the geometry-related parasitic effects; long narrow structures increase inductance, close parallel planes increase capacitance, etc. This is an area where using parametric sweeps and goal optimizing simulators to “right size” your port geometry can remove errors from your simulation results!
by: Chris Mesibov
by: Chris Mesibov
by: Chris Mesibov
by: Chris Mesibov
by: Peter Barrett
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