you are here:   / News & Insights / Engineering Advantage Blog / Adventures in High Speed PCB Design - Part 3

Engineering Advantage

Adventures in High Speed PCB Design - Part 3

November 15, 2016 By: Chris Mesibov

In the 1st installment of this story we explored the three phases of board development where simulation can be applied. The project kickoff, all of the project stakeholders, and review process were described. Here, we explore the designer’s challenges in ensuring the design is going to work prior to completion of the PCB artwork.

Simulation support for challenges in making SI measurements in the lab

  • It is difficult to implement board probing for signals with bandwidths greater than 5GHz without losing accuracy. Probing tends to insert a discontinuous ground situation that results in parasitic inductances in series with the probe. At the very least, this distorts your frequency response.
    • Simulation can help identify which measurement anomalies are real and which are a result of measurement error. TDR simulation versus TDR measurements, and frequency response analysis versus network analysis measurement.
  • The transmission line probing location is at the receiver device pin, not at the die where the load is located. Due to package and die parasitic effects, signal reflection and non-monotonicity might be measured but are not really being received at the actual device input.

Running circuit simulations on the transmission lines that include length of the trace, and Tx/Rx device, IBIS/AMI, or Spice model. A good device model (1) can predict the actual signal response at the die.
 


Your prototype boards have arrived in the lab, and now you and your team are spending long hours bringing the boards up. Getting the processor complex running is of first importance. Hopefully there are no issues with the DDR4 circuitry. Ultimately, the 1st boot code gets loaded and you can start working with some of the network interfaces, including the big network IC.

The board has hundreds of high speed digital signals. The timing margin of these signals need to be verified and, if necessary, FPGA modifications will be made. Also, signal integrity could greatly influence timing margins and any clock edge non-monotonicity could result in bad behavior. In addition, because your customer has tight EMI/EMC compliance requirements, you are concerned about edge rates. All of these concerns force you and you team to examine and plot almost every digital signal.

Using simulation to reduce test time

  • Ensuring your product is reliable not only maintains your company’s good name but also saves money.
  • To that end many companies invest in performing thorough test suites that cover all functions, document each waveform at room temperature and at the specified temperature limits. 
  • Verification by simulation can significantly reduce the measurement sets required.
  • For example, a data or address bus can be completely simulated (potentially 100 signals). These simulations could be automated using scripts for efficiency, and the results examined for consistency.  The measurement task can be reduced when correlation is made to a sample measurement.

Back to the story: Although not fully optimized yet, your big network IC is passing data between the network and client ports. You are getting bit errors and an investigation ensues. Using data loop backs, checking pre-emphasis settings at the transmitter and the equalization settings at the receiver are among the items to dig into. Another thing to check is the POL voltage accuracy. It seems that one of your nightmares has come true; voltage gradient under this IC is causing enough pin to pin voltage variation to exceed the vendor required voltage 0.85v +/-  2% spec. Clearly pin-to-pin current draw is not equivalent and there must be finite impedances on the power plane and/or ground planes causing the voltage drop. Had you performed a Power Integrity simulation you could had identified and resolved these problems before the PCB artwork was shipped. To add insult to injury, EMI/EMC compliance engineers are showing you radiated emission plots that are violating FCC limits at multiples of clock frequencies, but there are also peaks at frequencies not related to any known clock frequency or data rate on the board.

EMI/EMC simulation benefits

  • Simulating the far field can help identify edge rates that are unnecessarily fast and that could be adjusted in an FPGA.
  • Using a simulated near field result you can then simulate the boards enclosure shielding effectiveness.
  • I have used ANSYS SIwave to quickly analyze nearfield and far field radiation and ANSYS HFSS with the SIwave results to examine the shielding effectiveness of an enclosure.

PI Simulation Benefits

  • ANSYS SIwave is an example of a simulation tool that can expose deficiencies in your board’s power and ground layers.
  • Current vectors, current densities, voltage gradients, boards resonances can all be identified.

At this point another board spin is the plan. Clearly not enough simulation was performed during the layout process to help guide your design. Certainly, prior to this next PCB spin you’ll want to get assurances that all of the existing problems are resolved. 

This series of posts outlined some of the drama encountered during a complex electronics board development.  In future posts, I hope to discuss more details about what simulation activities and tools can be used to mitigate the drama!

 

 

 

 

 

[1] Device models from chip vendors can vary greatly in what they provide for accuracy.