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Adventures in High Speed PCB Design - Part 2

October 25, 2016 By: Chris Mesibov

In the 1st installment of this story we explored the three phases of board development where simulation can be applied.  The project kickoff, all of the project stakeholders, and review process were described.  Here, we explore the designer’s challenges in ensuring the design is going to work prior to completion of the PCB artwork.

Board layout

As the board layout proceeds, it’s a good idea to grab portions of the layout artwork and run some critical simulations. Perhaps you have a high performance network processor ASIC that has a network interface running 10s of GHz BW per lane.  This interface has the properties of microwave transmission lines, but your PCB material is only an improved version of FR4 as opposed to a ceramic substrate typically used at these frequencies. 

How well will the ultra-high speed network interface perform? Simulation is the best way to examine how the actual layout is affecting signal performance.

Ultra-High data rate simulation considerations:

  • Multi-lane cross talk should be simulated to ensure coupling is:
    • At least 10dB less than the cross talk in any connector.
    • Less than any system requirements on inter-symbol interference.
  • Insertion loss that includes losses introduced by the dielectric loss tangent and copper surface roughness.
  • Characteristic Impedance (Zo) verification as determined by the material properties and geometries provided by the PCB fabricator.
  • If p-to-n diff skew or lane-to-lane skew is important, electrical length simulation is required.
  • Impedance discontinuities due to connector pins and vias should be examined with simulation.
  • Simulated TDR and Eye diagrams can expose the impact of transmission line discontinuity on the results.

ANSYS HFSS and ANSYS 3D Layout are examples of effective tools to perform these simulations.

This network ASIC has many other interfaces that compete for PCB resources. It has a client side interface that is also multi-lane and operating at multiple Gbs per lane.  The IC also has multiple control interfaces, debug interfaces, and a JTAG/boundary scan interface.  Multiple low voltage, high current core Point of Load (POL) supplies, separate IO supplies, and special/complex power supply sequencing is required by the IC manufacturer for proper operation. The low voltage core supplies are at 0.85V, deliver 10’s of amps to multiple pins and are required to have low noise and tight pin to pin voltage compliance. 

Now your PCB layout CAD operator is complaining loudly that there are too many POL supplies and bypass capacitors to fit close to the IC. Then to boot, the CFD engineer has designed or specified heat sinks that require mounting holes that are eating up even more PCB real estate, further complicating critical routing. Even though you have a 24-layer PCB, with some 2oz Cu layers reserved for power planes, these layers look like Swiss cheese under the IC and now you are losing sleep over potential ground noise and voltage gradients. So you do your best to minimize current choke points by paralleling power copper areas where required.  

Power Integrity (PI) simulations could quickly expose these choke/pinch points as well as resonant areas that could impact EMI performance.

Power Integrity items to simulate

  • Voltage gradient map of power and ground planes.
  • Current crowding to identify “pinch points” and insufficient copper areas.
  • Plane impedance study to determine the contributions to switching noise.

EMI/EMC analysis to conduct

  • Determine the location of unpopulated board resonant points.
  • Analyze the optimization of bulk bypass capacitor placement to eliminate boards resonances.
  • Near field and far field emissions analysis.

 

Current density plots on ground and power planes


Prior to the release of the artwork, all the board stakeholders must perform reviews on the artwork for sign-off. Most of the reviewers are only looking for things that burned them in the past, but some are making critical observations and making crucial changes. The review ends when the project manager expresses concern with meeting the schedule, and the artwork files are FTPed to the fabricator. Now you have 2 weeks before your boards come in; One week for the blank board fabrication and the 2nd week for assembly and shipment to you. During this time, you spend most of your time finalizing the test document and completing the high speed passive transmission line simulations because you know there is no accurate way to measure these microwave range signals in the lab. 

In our next installment of this story I plan to delve into board test challenges and where simulation can reduce risk in measurement accuracy.